Intel PCI User Manual

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226
Software Developer’s Manual
Register Descriptions
Table 13-5. Status Register Bit Description
31
13 12
0
Reserved
Status
Field
Bit(s)
Initial 
Value
Description
FD
0
X
Link Full Duplex configuration Indication
When cleared, the Ethernet controller operates in half-duplex; 
when set, the Ethernet controller operates in Full duplex.
The FD provides the duplex setting status of the Ethernet 
controller as set by either Hardware Auto-Negotiation function, 
or by software.
LU
1
X
Link Up Indication
0b = no link config; 1b = link config. 
For TBI mode/internal SerDes operation: If Auto-Negotiation is 
enabled, this bit is set if a valid link is negotiated. If link is forced 
through CTRL.SLU, it reflects the status of this control bit.
For internal PHY mode of operation: Reflects the status of the 
internal link signal indicating a transition to a Link Up.
See 
 for more information about Auto-Negotiation.
Function ID
3:2
0b
Function ID.
Provides software a mechanism to determine the Ethernet 
controller function number (LAN identifier) for this MAC. Read 
as: [0b,0b] LAN A, [0b,1b] LAN B.
Note: These settings are only applicable to the 82546GB/EB.
For all other Ethernet controllers, set these bits to 0b.
TXOFF
4
X
Transmission Paused
When set, Indicates the transmit function is in Pause state due 
to reception of an XOFF pause frame when symmetrical flow 
control is enabled. It is cleared upon expiration of the pause 
timer, or receipt of an XON frame. Applicable only while working 
in full-duplex flow-control mode of operation.
TBIMODE
5
X
TBI Mode/internal SerDes Indication
When set, the Ethernet controller is configured to work in TBI 
mode/internal SerDes of operation. 
When clear, the Ethernet controller is configured to work in 
internal PHY mode.
Note: For the 82544GC/EI, reflects the status of the TBI_MODE 
input pin.
For all other Ethernet controllers, set this bit to 0b.