Intel PCI User Manual
230
Software Developer’s Manual
Register Descriptions
13.4.4
EEPROM Read Register
1
EERD (00014h; RW)
Table 13-7. EEPROM Read Register Bit Description
1.
Not applicable to the 82544GC/EI.
31 16
15 8
7 5
4
3 1
0
Data
Address
RSV.
DONE
RSV.
START
Field
Bit(s)
Initial
Value
Value
Description
START
0
0b
Start Read
Writing a 1b to this bit causes the EEPROM to read a (16-bit) word at
the address stored in the EE_ADDR field and then storing the result in
the EE_DATA field. This bit is self-clearing.
Writing a 1b to this bit causes the EEPROM to read a (16-bit) word at
the address stored in the EE_ADDR field and then storing the result in
the EE_DATA field. This bit is self-clearing.
Reserved
3:1
0b
Reserved. Reads as 0b.
DONE
4
0b
Read Done
Set to 1b when the EEPROM read completes.
Set to 0b when the EEPROM read is in progress.
Writes by software are ignored.
Set to 1b when the EEPROM read completes.
Set to 0b when the EEPROM read is in progress.
Writes by software are ignored.
Reserved
7:5
0b
Reserved. Reads as 0b.
ADDR
15:8
X
Read Address
This field is written by software along with Start Read to indicate the
word to read.
This field is written by software along with Start Read to indicate the
word to read.
DATA
31:16
X
Read Data. Data returned from the EEPROM read.