Intel PCI User Manual
Software Developer’s Manual
233
Register Descriptions
13.4.6
Extended Device Control Register
CTRL_EXT (00018h, R/W)
This register and the Device Control register (CTRL) controls the major operational modes for the
Ethernet controller. CTRL_EXT provides extended control of the Ethernet controller functionality
Ethernet controller. CTRL_EXT provides extended control of the Ethernet controller functionality
over the Device Control register (CTRL).
Note:
See
for the 82544GC/EI.
Table 13-10. CTRL_EXT Register Bit Description
31 - 24
23 - 16 15
0
Reserved
Extended Device Control Bits
Field
Bit(s)
Initial
Value
Value
Description
Reserved
1:0
0b
Reserved bits for the 82541xx and 82547GI/EI. Should be written
as 0b to ensure future compatibility.
as 0b to ensure future compatibility.
GPI_EN
3:0
0b
General Purpose Interrupt Enables
These bits determine whether the upper three software definable
pins SDP[7:6] and SDP[4] are mapped to the ICR.GPI interrupt
bits. These mappings are enabled only when the SDP[7:6] and
SDP[4] pins are configured as inputs through
CTRL_EXT.SWDPIOHI. Refer to
These bits determine whether the upper three software definable
pins SDP[7:6] and SDP[4] are mapped to the ICR.GPI interrupt
bits. These mappings are enabled only when the SDP[7:6] and
SDP[4] pins are configured as inputs through
CTRL_EXT.SWDPIOHI. Refer to
for SDP to ICR.GPI
bit mapping.
GPI_EN
3:2
0b
General Purpose Interrupt Enables for the 82541xx and 82547GI/
EI.
These bits determine whether the upper software definable pins
SDP[3:2] are mapped to the ICR.GPI interrupt bits. These
mappings are enabled only when the SDP[3:2] pins are configured
as inputs through CTRL_EXT.SWDPIOHI. Refer to
EI.
These bits determine whether the upper software definable pins
SDP[3:2] are mapped to the ICR.GPI interrupt bits. These
mappings are enabled only when the SDP[3:2] pins are configured
as inputs through CTRL_EXT.SWDPIOHI. Refer to
for
SDP to ICR.GPI bit mapping.
Reserved
4
0b
Reserved. Formally used as SDP4 pin data value. Reads as 0b.
PHYINT
5
0b
PHY Interrupt Value. When read, returns the current value of the
PHY internal interrupt status PHYINT.
Note: This is a reserved bit for the 82541xx and 82547GI/EI.
PHY internal interrupt status PHYINT.
Note: This is a reserved bit for the 82541xx and 82547GI/EI.
SDP6_DATA
SDP2_DATA
(82541xx and
82547GI/EI)
(82541xx and
82547GI/EI)
6
0b
1
SDP6[2] Data Value. Used to read (write) value of software-
controllable IO pin SDP6[2]. If SDP6[2] is configured as an output
(SDP6[2]_IODIR = 1b), this bit controls the value driven on the pin
(initial value EEPROM-configurable). If SDP6[2] is configured as
an input, reads return the current value of the pin.
controllable IO pin SDP6[2]. If SDP6[2] is configured as an output
(SDP6[2]_IODIR = 1b), this bit controls the value driven on the pin
(initial value EEPROM-configurable). If SDP6[2] is configured as
an input, reads return the current value of the pin.
SDP7_DATA
SDP3_DATA
(82541xx and
82547GI/EI)
(82541xx and
82547GI/EI)
7
0b
1
SDP7[3] Data Value. Used to read (write) value of software-
controllable IO pin SDP7[3]. If SDP7[3] is configured as an output
(SDP7[3]_IODIR = 1b), this bit controls the value driven on the pin
(initial value EEPROM-configurable). If SDP7[3] is configured as
an input, reads return the current value of the pin.
controllable IO pin SDP7[3]. If SDP7[3] is configured as an output
(SDP7[3]_IODIR = 1b), this bit controls the value driven on the pin
(initial value EEPROM-configurable). If SDP7[3] is configured as
an input, reads return the current value of the pin.
Reserved
9:8
01b
Reserved
Should be written as 01b to ensure future compatibility.
Should be written as 01b to ensure future compatibility.