Intel PCI User Manual
280
Software Developer’s Manual
Register Descriptions
Table 13-54. FCAH Register Bit Description
13.4.10
Flow Control Type
FCT (00030h; R/W)
This register contains the type field that hardware matches to recognize a flow control packet and
that hardware uses when transmitting a PAUSE packet to its remote node. Only the lower 16 bits of
that hardware uses when transmitting a PAUSE packet to its remote node. Only the lower 16 bits of
this register have meaning. This register should be programmed with 88_08h. The upper byte is
first on the wire FCT[15:8].
Table 13-55. FCT Register Bit Description
13.4.11
VLAN Ether Type
VET (00038h; R/W)
This register contains the type field hardware matches against to recognize an 802.1Q (VLAN)
Ethernet packet and uses when add and transmit VLAN Ethernet packets. To be compliant with the
Ethernet packet and uses when add and transmit VLAN Ethernet packets. To be compliant with the
802.3ac standard, this register should be programmed with the value 8100h. For VLAN
transmission the upper byte is first on the wire (VET[15:8]).
31
16 15
0
Reserved
FCAH
Field
Bit(s)
Initial
Value
Value
Description
FCAH
15:0
X
Flow Control Address High
Should be programmed with 0100h.
Should be programmed with 0100h.
Reserved
31:16
0b
Reserved
Should be written with 0b to ensure future compatibility.
Reads as 0b.
Should be written with 0b to ensure future compatibility.
Reads as 0b.
31
16 15
0
Reserved
FCT
Field
Bit(s)
Initial
Value
Value
Description
FCT
15:0
X
Flow Control Type
Should be programmed with 88_08h.
Should be programmed with 88_08h.
Reserved
31:16
0b
Reserved
Should be written with 0b to ensure future compatibility.
Reads as 0b.
Should be written with 0b to ensure future compatibility.
Reads as 0b.