Intel PCI User Manual
290
Software Developer’s Manual
Register Descriptions
RXT0
7
0b
Receiver Timer Interrupt
Set when the receiver timer expires.
The receiver timer is used for receiver descriptor packing. Timer
expiration flushes any accumulated descriptors and sets an
interrupt event when enabled.
Set when the receiver timer expires.
The receiver timer is used for receiver descriptor packing. Timer
expiration flushes any accumulated descriptors and sets an
interrupt event when enabled.
Reserved
8
0b
Reserved
Reads as 0b.
Reads as 0b.
MDAC
9
0b
MDI/O Access Complete
This bit is set when the MDI/O access is completed.
This bit is set when the MDI/O access is completed.
RXCFG
10
0b
Receiving /C/ ordered sets
Mapped to RXCW.RxConfig.
Sets when the hardware receives configuration symbols (/C/
codes). Software should enable this interrupt when forcing link.
When the link is forced, the link partner can begin to Auto-
Negotiate based, due to a reset or enabling of Auto-Negotiation.
The reception of /C/ codes causes an interrupt to software and the
proper hardware configuration might be set.
See
Mapped to RXCW.RxConfig.
Sets when the hardware receives configuration symbols (/C/
codes). Software should enable this interrupt when forcing link.
When the link is forced, the link partner can begin to Auto-
Negotiate based, due to a reset or enabling of Auto-Negotiation.
The reception of /C/ codes causes an interrupt to software and the
proper hardware configuration might be set.
See
for details. Only valid in internal SerDes
mode (TBI mode for the 82544GC/EI).
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
Reserved
11
0b
Reserved. Set this bit to 0b.
Not applicable to the 82544GC/EI.
Not applicable to the 82544GC/EI.
PHYINT
12
0b
PHY Interrupt (not applicable to the 82544GC/EI)
Set when the PHY generates an interrupt.
If bit 1 (PHYINT_EN) of the CTRL_EXT register (00018h) is set,
then this bit gets set.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
Set when the PHY generates an interrupt.
If bit 1 (PHYINT_EN) of the CTRL_EXT register (00018h) is set,
then this bit gets set.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
GPI_SDP6
GPI_SDP2
(82541xx and
82547GI/EI)
(82541xx and
82547GI/EI)
13
0b
General Purpose Interrupt on SDP6[2]. If GPI interrupt detection is
enabled on this pin (via CTRL_EXT), this interrupt cause is set
when the SDP6[2] is sampled high.
Not applicable to the 82544GC/EI.
enabled on this pin (via CTRL_EXT), this interrupt cause is set
when the SDP6[2] is sampled high.
Not applicable to the 82544GC/EI.
GPI_SDP7
GPI_SDP3
(82541xx and
82547GI/EI)
(82541xx and
82547GI/EI)
14
0b
General Purpose Interrupt on SDP7[3]. If GPI interrupt detection is
enabled on this pin (via CTRL_EXT), this interrupt cause is set
when the SDP7[3] is sampled high.
Not applicable to the 82544GC/EI.
enabled on this pin (via CTRL_EXT), this interrupt cause is set
when the SDP7[3] is sampled high.
Not applicable to the 82544GC/EI.
GPI
14:13,
11
11
0b
General Purpose Interrupts (82544GC/EI only)
These bits are mapped to the upper three SDP pins when they are
configured as inputs. Refer to
These bits are mapped to the upper three SDP pins when they are
configured as inputs. Refer to
.
TXD_LOW
2
15
0b
Transmit Descriptor Low Threshold hit.
Indicates that the descriptor ring has reached the threshold
specified in the Transmit Descriptor Control register.
Indicates that the descriptor ring has reached the threshold
specified in the Transmit Descriptor Control register.
SRPD
2
16
0b
Small Receive Packet Detected.
Indicates that a packet of size
Indicates that a packet of size
≤ RSRPD.SIZE register has been
detected and transferred to host memory. The interrupt is only
asserted if RSRPD.SIZE register has a non-zero value.
asserted if RSRPD.SIZE register has a non-zero value.
Field
Bit(s)
Initial
Value
Value
Description