Intel PCI User Manual

293

An interrupt is enabled if its corresponding mask bit is set to 1b, and disabled if its corresponding 

mask bit is set to 0b. A PCI interrupt is generated each time one of the bits in this register is set and 

the corresponding interrupt condition occurs. The occurrence of an interrupt condition is reflected 
by having a bit set in the Interrupt Cause Read Register (see 

).

A particular interrupt can be enabled by writing a 1b to the corresponding mask bit in this register. 

Any bits written with a 0b are unchanged. As a result, if software desires to disable a particular 

interrupt condition that had been previously enabled, it must write to the Interrupt Mask Clear 
Register (see 

) rather than writing a 0b to a bit in this register.

Reading this register returns bits that have an interrupt mask set.

For the 82547GI/EI, programmers need to first write (clear) the IMS and IMC registers due to a 

Hub Link bus being occupied. This results in an interrupt de-assertion message that can’t to be sent 

out. When a future interrupt assertion message is generated, two messages are re-ordered and sent 
out. This signals APIC that the 82547GI/EI is in a de-asserted state when it is actually in an 

asserted state, which causes a system dead lock. To avoid a system dead lock, first clear the IMS 
and IMC registers by writing FFFFh and then re-assert IRQ enable.

GPI

14:11

X

Sets General Purpose Interrupts (82544GC/EI only).

GPI

14:13

X

Sets General Purpose Interrupts.

TXD_LOW

15

X

Transmit Descriptor Low Threshold Hit. Not applicable to the 
82544GC/EI.

SRPD

16

X

Small Receive Packet Detected and Transferred. Not applicable 
to the 82544GC/EI.

Reserved

31:17

X

Reserved
Should be written with 0b to ensure future compatibility.

Reserved

IMS Bits

TXDW

0

X

Sets mask for Transmit Descriptor Written Back.

TXQE

1

X

Sets mask for Transmit Queue Empty.

LSC

2

X

Sets mask for Link Status Change.