Intel PCI User Manual
346
Software Developer’s Manual
Register Descriptions
Table 13-111. XOFFTXC Register Bit Description
13.7.20
FC Received Unsupported Count
FCRUC (04058h; R)
This register counts the number of unsupported flow control frames that are received.
The FCRUC counter increments when a flow control packet is received that matches either the
reserved flow control multicast address (in FCAH/L) or the MAC station address, and has a
matching flow control type field match (to the value in FCT), but has an incorrect opcode field.
This register only increments if receives are enabled.
This register only increments if receives are enabled.
Table 13-112. FCRUC Register Bit Description
13.7.21
Packets Received (64 Bytes) Count
PRC64 (0405Ch; R)
This register counts the number of good packets received that are exactly 64 bytes (from
<Destination Address> through <CRC>, inclusively) in length. Packets that are counted in the
<Destination Address> through <CRC>, inclusively) in length. Packets that are counted in the
Missed Packet Count register are not counted in this register. This register does not include
received flow control packets and increments only if receives are enabled.
31
0
XOFFTXC
Field
Bit(s)
Initial
Value
Value
Description
XOFFTXC
31:0
0b
Number of XOFF packets transmitted.
31
0
FCRUC
Field
Bit(s)
Initial
Value
Value
Description
FCRUC
31:0
0b
Number of unsupported flow control frames received.