Intel PCI User Manual

389

This section describes the new features that have been added to the PCI/PCI-X Family of Gigabit 
Ethernet Controllers from its predecessor, the 82544EI/82544GC and highlights its registers that 

have been changed.

Following is a list of the new features in the Ethernet controller, along with sections in this manual 

that describe these features in detail:

•

. The 82546GB/EB architecture includes two instances of both 

the MAC and PHY. The Ethernet controller contains a single PCI/PCI-X interface so that each 

of the logical LAN devices appear as a distinct PCI/PCI-X bus device (see 

).

•

. The Ethernet controller supports IP/TCP/UDP receive checksum offload for 

IPv6 packets, IPv6 wakeup filters, and IPv6 TCP segmentation (see 

).

•

. The Ethernet controller has the following new interrupt generation 

features to enhance driver performance:

— Packet timers and absolute delay timers for transmit and receive (see 

).

— Short packet detection interrupts (see 

).

— Transmit descriptor low interrupts (see 

).

— Interrupt throttling control to limit maximum interrupt rate (see 

).

— Acknowledge interrupts by writing 1b’s to the ICR (see 

).

•

. Because the 82546GB/EB has two MAC/PHY instances that could 

potentially access the EEPROM at the same time, a semaphore has been added to gate access. 
In addition, the EERD now allows easy EEPROM access (see 

).

•

. The Ethernet controller introduces manageability for ASF 1.0 and AOL 2.0.

•

. The Ethernet controller enables software to customize LED displays (see 

).

•

. The internal copper PHY features 10/100/1000-BaseT signalling and is 

capable of performing intelligent power-management based on both the system power-state 
and LAN energy-detection (detection of unplugged cables). See 

.