Intel PCI User Manual
Receive and Transmit Description
Software Developer’s Manual
31
3.2.7.3
Receive Descriptor Minimum Threshold (ICR.RXDMT)
The minimum descriptor threshold helps avoid descriptor under-run by generating an interrupt
when the number of free descriptors becomes equal to the minimum amount defined in
RCTL.RDMTS (measured as a fraction of the receive descriptor ring size).
RCTL.RDMTS (measured as a fraction of the receive descriptor ring size).
3.2.7.4
Receiver FIFO Overrun
FIFO overrun occurs when hardware attempts to write a byte to a full FIFO. An overrun could
indicate that software has not updated the tail pointer to provide enough descriptors/buffers, or that
the PCI bus is too slow draining the receive FIFO. Incoming packets that overrun the FIFO are
dropped and do not affect future packet reception.
dropped and do not affect future packet reception.
3.2.8
82544GC/EI Receive Interrupts
The presence of new packets is indicated by the following:
•
Absolute timer (RDTR) — A predetermined amount of time has elapsed since the first packet
received after the hardware timer was written (specifically, after the last packet data byte was
received after the hardware timer was written (specifically, after the last packet data byte was
written to memory); this also flushes any accumulated descriptors to memory. Software can set
the timer value to 0b if it wants to be notified each time a new packet has been stored in
memory.
Writing the absolute timer with its high order bit 1 forces an explicit flush of any partial cache
memory.
Writing the absolute timer with its high order bit 1 forces an explicit flush of any partial cache
lines. Hardware writes all used descriptors to memory and updates the globally visible value of
the head pointer.
the head pointer.
In addition, hardware provides the following interrupts:
•
Receive Descriptor Minimum Threshold (ICR.RXDMT)
The minimum descriptor threshold helps avoid descriptor underrun by generating an interrupt
when the number of free descriptors becomes equal to the minimum. It is measured as a
The minimum descriptor threshold helps avoid descriptor underrun by generating an interrupt
when the number of free descriptors becomes equal to the minimum. It is measured as a
fraction of the receive descriptor ring size.
•
Receiver FIFO Overrun (ICR.RXO)
FIFO overrun occurs when hardware attempts to write a byte to a full FIFO. An overrun could
FIFO overrun occurs when hardware attempts to write a byte to a full FIFO. An overrun could
indicate that software has not updated the tail pointer to provide enough descriptors/buffers, or
that the PCI bus is too slow draining the receive FIFO. Incoming packets that overrun the
that the PCI bus is too slow draining the receive FIFO. Incoming packets that overrun the
FIFO are dropped and do not affect future packet reception.
3.2.9
Receive Packet Checksum Offloading
The Ethernet controller supports the offloading of three receive checksum calculations: the Packet
Checksum, the IP Header Checksum, and the TCP/UDP Checksum.
Checksum, the IP Header Checksum, and the TCP/UDP Checksum.
Note: IPv6 packets do not have IP checksums.