Intel PCI User Manual
84
Software Developer’s Manual
PCI Local Bus Interface
4.1.3.1.3
Message Control
15 8
7
6 4
3 1
0
Reserved
64b
Multiple
Enable
Multiple
Capable
En
Bits
Read/
Write
Initial
Value
Value
Description
0
R
0b
MSI Enable. If 1b, Message Signaled Interrupts
a
are enabled and the
Ethernet controller generates Message Signaled Interrupts instead of
asserting INTA#.
asserting INTA#.
3:1
R
0b
Multiple Message Capable. Indicates the number of messages
requested. The Ethernet controller only requests one message.
Register
requested. The Ethernet controller only requests one message.
Register
Number of messages
0
1
1 2
2 4
3 8
4 16
5 32
6 Reserved
7 Reserved
2 4
3 8
4 16
5 32
6 Reserved
7 Reserved
6:4
RW
0b
Multiple Message Enable. Written by the system to indicate the
number of messages allocated. Since the Ethernet controller only
supports one message, the system should never write a value other
than 0b.
number of messages allocated. Since the Ethernet controller only
supports one message, the system should never write a value other
than 0b.
7
R
1b
64-bit capable. A value of 1b indicates that the Ethernet controller is
capable of generating 64-bit message addresses.
capable of generating 64-bit message addresses.
15:8
R
0b
Reserved. Reads as 0b.
a.
Not applicable to the 82541xx or 82547GI/EI.