Intel PCI-X User Manual

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The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts. However, it 
might be necessary to ensure that no completed transmit remains unnoticed for too long an interval 

in order ensure timely release of transmit buffers. This register can be used to ENSURE that a 

transmit interrupt occurs at some predefined interval after a transmit is completed. Like the 
delayed-transmit timer, the absolute transmit timer ONLY applies to transmit descriptor operations 

where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is 

requested (IDE is set).

This feature operates by initiating a countdown timer upon successfully transmitting the buffer. 
When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated. The occurrence 

of either an immediate (non-scheduled) or delayed transmit timer (TIDV) expiration interrupt halts 

the TADV timer and eliminates any spurious second interrupts.

Setting the value to 0b disables the transmit absolute delay function. If an immediate (non-
scheduled) interrupt is desired for any transmit descriptor, the descriptor IDE should be set to 0b.

This register specifies fields affecting the Ethernet controller behavior during TCP Segmentation 

operations. Values are specified in bytes. For normal (non TCP Segmentation) operations, the 

Ethernet controller’s transmit DMA never begins servicing an individual data descriptor unless the 
transmit Packet Buffer has sufficient room to accept all of the data associated with the descriptor. 

However, for TCP Segmentation operations, it might be desirable to use a data descriptor that 

refers to a larger contiguous buffer in host memory than is actually allocated for the transmit Packet 
Buffer. For TCP segmentation, then, the transmit DMA is able to initiate smaller transfers than the 

entire descriptor’s data length field.

TSPBP

TSMT

TSMT

15:0

0400h

TCP Segmentation Minimum Transfer

TSPBP

31:16

0100h

TCP Segmentation Packet Buffer Padding