Renesas SH7264 User Manual
Section 2 CPU
Page 80 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
CLIPS.B Rn
0100nnnn10010001
When Rn > (H'0000007F),
(H'0000007F)
Rn, 1 CS
when Rn < (H'FFFFFF80),
(H'FFFFFF80)
Rn, 1 CS
1
Yes
CLIPS.W Rn
0100nnnn10010101
When Rn > (H'00007FFF),
(H'00007FFF)
Rn, 1 CS
When Rn < (H'FFFF8000),
(H'FFFF8000)
Rn, 1 CS
1
Yes
CLIPU.B Rn
0100nnnn10000001
When Rn > (H'000000FF),
(H'000000FF)
Rn, 1 CS
1
Yes
CLIPU.W Rn
0100nnnn10000101
When Rn > (H'0000FFFF),
(H'0000FFFF)
Rn, 1 CS
1
Yes
DIV1 Rm,Rn
0011nnnnmmmm0100
1-step division (Rn
Rm)
1
Calcu-
lation
result
Yes Yes Yes
DIV0S Rm,Rn
0010nnnnmmmm0111
MSB of Rn
Q,
MSB of Rm
M, M ^ Q T
1 Calcu-
lation
result
Yes Yes Yes
DIV0U
0000000000011001
0
M/Q/T
1
0
Yes
Yes
Yes
DIVS R0,Rn
0100nnnn10010100
Signed operation of Rn
R0
Rn 32 32 32 bits
36
Yes
DIVU R0,Rn
0100nnnn10000100
Unsigned operation of Rn
R0
Rn 32 32 32 bits
34
Yes
DMULS.L Rm,Rn
0011nnnnmmmm1101
Signed operation of Rn
Rm
MACH, MACL
32
32 64 bits
2
Yes
Yes
Yes
DMULU.L Rm,Rn
0011nnnnmmmm0101
Unsigned operation of Rn
Rm
MACH, MACL
32
32 64 bits
2
Yes
Yes
Yes
DT Rn
0100nnnn00010000
Rn
– 1
Rn
When Rn is 0, 1
T
When Rn is not 0, 0
T
1 Compa
-rison
result
Yes Yes Yes
EXTS.B Rm,Rn
0110nnnnmmmm1110
Byte in Rm is
sign-extended
Rn
1
Yes
Yes
Yes
EXTS.W Rm,Rn
0110nnnnmmmm1111
Word in Rm is
sign-extended
Rn
1
Yes
Yes
Yes