Renesas SH7264 User Manual

 

Section 27   Video Display Controller 3 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1571 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

20 BURST_MODE

_MAIN 

0 

R/W 

Selects the mode of transfer through the IV1-BUS 
in the video receiving block. Writing out to the 
areas except the large-capacity on-chip RAM 
requires this bit to be set to 0. 

0: 16-byte burst transfer 

1: 128-byte burst transfer 

19, 18 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

17 ENDIAN_DISP 

0 R/W 

Specifies 

the 

endian for the IV2-BUS in the video 

supplying block. 

0: Big endian 

1: Little endian 

16 ENDIAN_MAIN 

0 R/W 

Specifies 

the 

endian for the IV1-BUS in the video 

supplying block. 

0: Big endian 

1: Little endian 

15 

 All 

0 

R 

Reserved 

This bit is always read as 0. The write value 
should always be 0. 

14 

SEL_EXSYNC  0 

R/W 

Enables the external input sync signal. 

0: Disabled 

1: Enabled 

13 SEL_656601 

0 R/W 

Specifies 

the format of the input video. 

0: BT.656 input (be sure to set SEL_EXSYNC = 0)

1: BT.601 input (be sure to set SEL_EXSYNC = 1)

12 

SEL_525625 

0 

R/W 

Specifies the number of lines for the input video. 

0: 525 lines (NTSC) 

1: 625 lines (PAL) 

11 to 5 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0.