Renesas SH7264 User Manual
Section 28 Sampling Rate Converter
Page 1646 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
9
OED
0
R/W
Output Data Endian
Specifies the endian format of the output data.
0: Big endian
1: Little endian
8
OEN
0
R/W
Output Data FIFO Full Interrupt Enable
Enables/disables the output data FIFO full interrupt
request to be issued when the number of data units in
the output FIFO becomes equal to or greater than the
number specified by the OFTRG1 and OFTRG0 bits,
thus resulting in the OINT bit in the status register
(SRCSTAT) being set to 1.
request to be issued when the number of data units in
the output FIFO becomes equal to or greater than the
number specified by the OFTRG1 and OFTRG0 bits,
thus resulting in the OINT bit in the status register
(SRCSTAT) being set to 1.
0: Output data FIFO full interrupt is disabled.
1: Output data FIFO full interrupt is enabled.
7 to 2
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
1, 0
OFTRG[1:0]
00
R/W
Output FIFO Data Trigger Number
Specifies the condition in terms of the number on
which the OINT bit in the status register (SRCSTAT)
is set to 1. When the number of data units in the
output FIFO becomes equal to or greater than the
number listed below, the OINT bit is set to 1.
which the OINT bit in the status register (SRCSTAT)
is set to 1. When the number of data units in the
output FIFO becomes equal to or greater than the
number listed below, the OINT bit is set to 1.
For channel 0:
00: 1
01: 4
10: 8
11: 12
For channel 1:
00: 1
01: 1
10: 2
11: 3