Renesas SH7264 User Manual

Page of 2152
 
Section 6   Exception Handling 
 
Page 136 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
Exception Sources 
Vector 
Numbers 
Vector Table Address Offset 
External interrupts (IRQ, PINT),  
on-chip peripheral module interrupts* 
64
  : 
511 
H'00000100 to H'00000103 
 : 
H'000007FC to H'000007FF 
Note:  *  The vector numbers and vector table address offsets for each external interrupt and on-
chip peripheral module interrupt are given in table 7.4 in section 7, Interrupt Controller. 
 
Table 6.4 
Calculating Exception Handling Vector Table Addresses 
Exception Source 
Vector Table Address Calculation 
Resets 
Vector table address = (vector table address offset) 
 
= (vector number) 
 4 
Address errors, register bank 
errors, interrupts, instructions 
Vector table address = VBR + (vector table address offset) 
 
= VBR + (vector number) 
 4 
Notes:  1.  Vector table address offset: See table 6.3. 
 
2.  Vector number: See table 6.3.