Renesas SH7264 User Manual
Section 8 Cache
Page 222 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Longword 0
Longword 1
Longword 2
Longword 3
A (31 to 4)
A (31 to 4):
Longword 0 to 3:
Longword 0 to 3:
Physical address written to external memory (upper three bits are 0)
One line of cache data to be written to external memory
One line of cache data to be written to external memory
Figure 8.3 Write-Back Buffer Configuration
Operations in sections 8.3.2 to 8.3.5 are summarized in table 8.8.
Table 8.8
Cache Operations
Cache
CPU
Cycle
Hit/
Miss
Write-Back Mode/
Write-Through
Mode U
Bit
Access to External Memory
or Large-Capacity On-Chip
RAM (Through Internal Bus) Cache Contents
Instruction
cache
Instruction
fetch
Hit
Not generated
Not updated
Miss
Cache update cycle is
generated
Updated to new values by cache
update cycle
Operand
cache
Prefetch/
read
Hit
Either mode is
available
x
Not generated
Not updated
Miss
Write-through
mode
Cache update cycle is
generated
Updated to new values by cache
update cycle
Write-back mode
0
Cache update cycle is
generated
Updated to new values by cache
update cycle
1
Cache update cycle is
generated. Then write-back
cycle in write-back buffer is
generated.
Updated to new values by cache
update cycle
Write
Hit
Write-through
mode
Write cycle CPU issues is
generated.
Updated to new values by write
cycle the CPU issues
Write-back mode
x
Not generated
Updated to new values by write
cycle the CPU issues
Miss
Write-through
mode
Write cycle CPU issues is
generated.
Not updated*
Write-back mode
0
Cache update cycle is
generated
Updated to new values by cache
update cycle. Subsequently
updated again to new values in
write cycle CPU issues.
1
Cache update cycle is
generated. Then write-back
cycle in write-back buffer is
generated.
Updated to new values by cache
update cycle. Subsequently
updated again to new values in
write cycle CPU issues.