Renesas SH7264 User Manual
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00
Page 365 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state
synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5
cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals
(
synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5
cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals
(
BS, CSn, RAS, CAS, CKE, DQMx, WEn, RD, and RD/WR) are placed in the high-impedance
state at subsequent rising edges of CKIO. These bus control signals are driven high one or more
cycles before they are placed in the high-impedance state. Bus request signals are sampled at the
falling edge of CKIO. Note that CKE,
cycles before they are placed in the high-impedance state. Bus request signals are sampled at the
falling edge of CKIO. Note that CKE,
RAS, and CAS can be continued to be driven at the
previous value even in the bus-released state by setting the HIZCNT bit in CMNCR.
The sequence for reclaiming the bus mastership from an external device is described below. 1.5
cycles after the negation of
cycles after the negation of
BREQ is detected at the falling edge of CKIO, the bus control signals
are driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The
fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the
rising edge of the
fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the
rising edge of the
CKIO where address and data signals are driven. Figure 9.47 shows the bus
arbitration timing.
When it is necessary to refresh SDRAM while releasing the bus mastership, the bus mastership
should be returned. If the bus mastership is not returned for a specified refreshing period or longer,
the contents of SDRAM cannot be guaranteed because a refreshing cannot be executed.
should be returned. If the bus mastership is not returned for a specified refreshing period or longer,
the contents of SDRAM cannot be guaranteed because a refreshing cannot be executed.
While releasing the bus mastership, the SLEEP instruction (to enter sleep mode, deep standby
mode, or software standby mode), as well as a manual reset, cannot be executed until the LSI
obtains the bus mastership.
mode, or software standby mode), as well as a manual reset, cannot be executed until the LSI
obtains the bus mastership.
The
BREQ input signal is ignored in software standby mode or deep standby mode and the BACK
output signal is placed in the high impedance state. If the bus mastership request is required in this
state, the bus mastership must be released by pulling down the
state, the bus mastership must be released by pulling down the
BACK pin to enter software
standby mode or deep standby mode.
The bus mastership release (
BREQ signal for high level negation) after the bus mastership request
(
BREQ signal for low level assertion) must be performed after the bus usage permission (BACK
signal for low level assertion). If the
BREQ signal is negated before the BACK signal is asserted,
only one cycle of the
BACK signal is asserted depending on the timing of the BREQ signal to be
negated and this may cause a bus contention between the external device and the LSI.