Renesas SH7264 User Manual

 

Section 15   Serial Communication Interface with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 719 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

3 

STOP 

0 

R/W 

Stop Bit Length 

Selects one or two bits as the stop bit length in 
asynchronous mode. This setting is used only in 
asynchronous mode. It is ignored in clock synchronous 
mode because no stop bits are added. 

When receiving, only the first stop bit is checked, 
regardless of the STOP bit setting. If the second stop 
bit is 1, it is treated as a stop bit, but if the second stop 
bit is 0, it is treated as the start bit of the next incoming 
character. 

0: One stop bit 

When transmitting, a single 1-bit is added at the end 
of each transmitted character. 

1: Two stop bits 

When transmitting, two 1 bits are added at the end of 
each transmitted character. 

2 

 0 

R 

Reserved 

This bit is always read as 0. The write value should 
always be 0. 

1, 0 

CKS[1:0] 

00 

R/W 

Clock Select 

Select the internal clock source of the on-chip baud rate 
generator. For further information on the clock source, 
bit rate register settings, and baud rate, see section 
15.3.8, Bit Rate Register (SCBRR). 

00: P

 

01: P

/4 

10: P

/16 

11: P

/64 

Note: P

: Peripheral clock