Renesas SH7264 User Manual
Section 15 Serial Communication Interface with FIFO
Page 748 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(2) Clock Synchronous Mode (SH7262: Channels 0 to 2, SH7264: Channels 0 to 3)
The transmission/reception format has a fixed 8-bit data length.
In receiving, it is possible to detect overrun errors (ORER).
An internal or external clock can be selected as the clock source.
In receiving, it is possible to detect overrun errors (ORER).
An internal or external clock can be selected as the clock source.
When an internal clock is selected, this module operates using the clock of the on-chip
baud rate generator, and outputs this clock to external devices as the synchronous clock.
baud rate generator, and outputs this clock to external devices as the synchronous clock.
When an external clock is selected, this module operates on the input external synchronous
clock not using the on-chip baud rate generator.
clock not using the on-chip baud rate generator.
Table 15.9 SCSMR Settings and Communication Formats
SCSMR Settings
Communication Format
Bit 7
C/
C/
A
Bit 6
CHR
CHR
Bit 5
PE
PE
Bit 3
STOP Mode
STOP Mode
Data Length
Parity Bit
Stop Bit Length
0 0 0 0 Asynchronous
8
bits
Not
set
1
bit
1
2
bits
1
0
Set
1
bit
1
2
bits
1
0
0
7 bits
Not set
1 bit
1
2
bits
1
0
Set
1
bit
1
2
bits
1 x x x Clock
synchronous
8 bits
Not set
None
[Legend]
x: Don't
care