Renesas SH7264 User Manual
Section 18 Serial Sound Interface
Page 912 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
5, 4
RTRG[1:0] 00
R/W
Receive Data Trigger Count
These bits specify the received data count (specified
receive trigger count) at which the RDF flag in the FIFO
status register (SSIFSR) is set during reception.
receive trigger count) at which the RDF flag in the FIFO
status register (SSIFSR) is set during reception.
The RDF flag is set to 1 when the received data count
in the receive FIFO data register (SSIFRDR) is equal to
or more than the specified trigger count shown below.
in the receive FIFO data register (SSIFRDR) is equal to
or more than the specified trigger count shown below.
00: 1
01: 2
10: 4
11: 6
3
TIE
0
R/W
Transmit Interrupt Enable
Enables or disables generation of transmit data empty
interrupt (TXI) requests during transmission when serial
transmit data is transferred from the transmit FIFO data
register (SSIFTDR) to the transmit data register
(SSITDR), the data count of the transmit FIFO data
register is less than the specified transmit trigger count,
and the TDE flag in the FIFO status register (SSIFSR)
is set to 1.
interrupt (TXI) requests during transmission when serial
transmit data is transferred from the transmit FIFO data
register (SSIFTDR) to the transmit data register
(SSITDR), the data count of the transmit FIFO data
register is less than the specified transmit trigger count,
and the TDE flag in the FIFO status register (SSIFSR)
is set to 1.
0: Transmit data empty interrupt (TXI) request is
disabled
1: Transmit data empty interrupt (TXI) request is
enabled*
Note: * TXI can be cleared by clearing either the TDE
flag (see the description of the TDE bit for
details) or TIE bit.
details) or TIE bit.