Renesas SH7264 User Manual

 

Section 19   Serial I/O with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 953 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

3 TFOVF 

0  R/W 

Transmit 

FIFO 

Overflow 

0: No transmit FIFO overflow 

1: Transmit FIFO overflow 

A transmit FIFO overflow means that there has been an 
attempt to write to SITDR when the transmit FIFO is full. 

When an overflow of the transmit FIFO occurs, the write 
which caused the overflow is invalid. 

  This bit is valid when the TXE bit in SICTR is 1.  
  When this bit is set to 1, it is cleared to 0 by this 

module. Writing 0 to this bit is invalid. 

2 TFUDF 

0  R/W 

Transmit 

FIFO 

Underflow 

0: No transmit FIFO underflow 

1: Transmit FIFO underflow 

A transmit FIFO underflow means that loading for 
transmission has occurred when the transmit FIFO is 
empty. 

When a transmit FIFO underflow occurs, this module 
repeatedly sends the previous transmit data. 

  This bit is valid when the TXE bit in SICTR is 1.  
  When this bit is set to 1, it is cleared to 0 by this 

module. Writing 0 to this bit is invalid. 

1 RFUDF 

0  R/W 

Receive 

FIFO 

Underflow 

0: No receive FIFO underflow 

1: Receive FIFO underflow 

A receive FIFO underflow means that reading of SIRDR 
has occurred when the receive FIFO is empty. 

When a receive FIFO underflow occurs, the value of data 
read from SIRDR is not guaranteed. 

  This bit is valid when the RXE bit in SICTR is 1.  
  When this bit is set to 1, it is cleared to 0 by this 

module. Writing 0 to this bit is invalid.