Renesas R5S72623 User Manual
Section 23 CD-ROM Decoder
R01UH0134EJ0400 Rev. 4.00
Page 1235 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
23.3.47
CD-ROM Decoder Reset Status Register (RSTSTAT)
The CD-ROM decoder reset status register (RSTSTAT) indicates that the RAM in the CD-ROM
decoder has been cleared.
decoder has been cleared.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
RAM
CLRST
-
-
-
-
-
-
-
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
7
RAMCLRST
0
R
This bit is set to 1 on completion of RAM clearing after
the RAMRST bit in ROMDECRST is set to 1. The bit is
cleared by writing a 0 to the RAMRST bit.
cleared by writing a 0 to the RAMRST bit.
6 to 0
All
0
R
Reserved
These bits are always read as 0 and cannot be
modified.
modified.
23.3.48
Serial Sound Interface Data Control Register (SSI)
The serial sound interface data control register (SSI) provides various settings related to the data
stream. For the operation corresponding to the setting of this register, refer to section 23.4.1,
Endian Conversion for Data in the Input Stream.
stream. For the operation corresponding to the setting of this register, refer to section 23.4.1,
Endian Conversion for Data in the Input Stream.
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
BYTEND BITEND
BUFEND0[1:0]
BUFEND1[1:0]
-
-
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
7
BYTEND
0
R/W
Specifies the endian of input data from the serial sound
interface.
When this bit is set to 1, byte 0 and byte 1 in
STRMDIN0 are swapped. This is the same for
STRMDIN2.
STRMDIN2.