Renesas R5S72623 User Manual
Section 26 USB 2.0 Host/Function Module
Page 1368 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
26.3.8
FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)
CFIFOSEL, D0FIFOSEL and D1FIFOSEL are registers that assign the pipe to the FIFO port, and
control access to the corresponding port.
control access to the corresponding port.
The same pipe should not be specified by the CURPIPE bits in CFIFOSEL, D0FIFOSEL and
D1FIFOSEL. When the CURPIPE bits in D0FIFOSEL and D1FIFOSEL are cleared to B'000, no
pipe is selected.
D1FIFOSEL. When the CURPIPE bits in D0FIFOSEL and D1FIFOSEL are cleared to B'000, no
pipe is selected.
The pipe number should not be changed while the DMA transfer is enabled.
These registers are initialized by a power-on reset.
(1) CFIFOSEL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R
R/W
R
R
R/W
R
R/W
R/W
R/W
R/W
R/W*
RCNT
REW
—
—
MBW[1:0]
—
—
—
ISEL
BIGEND
—
CURPIPE[3:0]
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
15
RCNT
0
R/W
Read Count Mode
Specifies the read mode for the value in the DTLN
bits in CFIFOCTR.
bits in CFIFOCTR.
0: The DTLN bit is cleared when all of the receive
data has been read from the CFIFO.
(In double buffer mode, the DTLN bit value is
cleared when all the data has been read from a
single plane.)
cleared when all the data has been read from a
single plane.)
1: The DTLN bit is decremented when the receive
data is read from the CFIFO.