Renesas R5S72623 User Manual
Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00
Page 1583 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.7
Timing Control Register 1 for Vertical Sync Signal for Video
(VIDEO_VSYNC_TIM1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
VIDEO_VSYNC_START1_TOP[9:0]
VIDEO_VSYNC_START1_BTM[9:0]
-
-
-
-
-
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 26
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
25 to 16
VIDEO_VSYNC
_START1_
TOP [9:0]
_START1_
TOP [9:0]
H'000
R/W
These bits specify the reference Vsync position in
the TOP field in number of lines.
the TOP field in number of lines.
15 to 10
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
9 to 0
VIDEO_VSYNC
_START1_
BTM[9:0]
_START1_
BTM[9:0]
H'000
R/W
These bits specify the reference Vsync position in
the BOTTOM field in number of lines.
the BOTTOM field in number of lines.