Renesas R5S72623 User Manual
Section 28 Sampling Rate Converter
R01UH0134EJ0400 Rev. 4.00
Page 1643 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
28.2.3
Input Data Control Register (SRCIDCTRL)
SRCIDCTRL is a 16-bit readable/writable register that specifies the endian format of input data,
enables/disables the interrupt requests, and specifies the triggering number of data units.
enables/disables the interrupt requests, and specifies the triggering number of data units.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
R
R
R
R
R
R
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
IED
IEN
⎯
⎯
⎯
⎯
⎯
⎯
IFTRG[1:0]
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
15 to 10
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
9
IED
0
R/W
Input Data Endian
Specifies the endian format of the input data.
0: Big endian
1: Little endian
8
IEN
0
R/W
Input Data FIFO Empty Interrupt Enable
Enables/disables the input data FIFO empty interrupt
request to be issued when the number of data units in
the input FIFO becomes equal to or smaller than the
triggering number specified by the IFTRG1 and
IFTRG0 bits, thus resulting in the IINT bit in the status
register (SRCSTAT) being set to 1.
request to be issued when the number of data units in
the input FIFO becomes equal to or smaller than the
triggering number specified by the IFTRG1 and
IFTRG0 bits, thus resulting in the IINT bit in the status
register (SRCSTAT) being set to 1.
0: Input data FIFO empty interrupt is disabled.
1: Input data FIFO empty interrupt is enabled.
7 to 2
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.