Renesas R5S72623 User Manual
Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00
Page 143 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
6.3.2
Address Error Exception Handling
When an address error occurs, the bus cycle in which the address error occurred ends. When the
executing instruction then finishes, address error exception handling starts. The CPU operates as
follows:
executing instruction then finishes, address error exception handling starts. The CPU operates as
follows:
1. The exception service routine start address which corresponds to the address error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
6.4
Register Bank Errors
6.4.1
Register Bank Error Sources
(1) Bank Overflow
In the state where saving has already been performed to all register bank areas, bank overflow
occurs when acceptance of register bank overflow exception has been set by the interrupt
controller (the BOVE bit in IBNR of the interrupt controller is set to 1) and an interrupt that uses a
register bank has occurred and been accepted by the CPU.
occurs when acceptance of register bank overflow exception has been set by the interrupt
controller (the BOVE bit in IBNR of the interrupt controller is set to 1) and an interrupt that uses a
register bank has occurred and been accepted by the CPU.
(2) Bank Underflow
Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving
has not been performed to register banks.
has not been performed to register banks.