Renesas R5S72623 User Manual

 
Section 33   Power-Down Modes 

Page 1790 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

1 

RAME1 

1 

R/W 

RAM Enable 1 (corresponding area: page 1* in high-
speed on-chip RAM) 

0: Access to page 1 is disabled. 

1: Access to page 1 is enabled. 

0 

RAME0 

1 

R/W 

RAM Enable 0 (corresponding area: page 0* in high-
speed on-chip RAM) 

0: Access to page 0 is disabled. 

1: Access to page 0 is enabled. 

Note:  *  For addresses in each page, see section 31, On-Chip RAM. 

 

SYSCR2 is an 8-bit readable/writable register that enables or disables writing to a specified page 
in the high-speed on-chip RAM. 

When an RAMEn (n = 0 to 3) bit is set to 1, writing to page n is enabled. When an RAMEn bit is 
cleared to 0,writing to page n is ignored. The initial value of an RAMEn bit is 1.  

Note that when clearing the RAMWEn bit to 0, be sure to execute an instruction to read from or 
write to the same arbitrary address in each page before setting the RAMWEn bit. If such an 
instruction is not executed, the data last written to page n may not be written to the high-speed on-
chip RAM.  

SYSCR2 should be set with a program located in an area other than the high-speed on-chip RAM. Furthermore, an 

instruction to read SYSCR2 should be located immediately after the instruction to write to SYSCR2. If not, normal access 

is not guaranteed. 

Note:  When writing to this register, see section 33.4, Usage Notes. 

7

6

5

4

3

2

1

0

Bit:

Initial value:

R/W:

1

1

1

1

1

1

1

1

R

R

R

R

R/W

R/W

R/W

R/W

-

-

-

-

RAM
WE3

RAM
WE2

RAM
WE0

RAM
WE1