Renesas R5S72623 User Manual
Section 7 Interrupt Controller
Page 170 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
7.3.7
PINT Interrupt Request Register (PIRR)
PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to
PINT0.
PINT0.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
-
-
-
-
-
-
-
-
PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
15 to 8
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
7
PINT7R
0
R
PINT Interrupt Request
These bits indicate the status of the PINT7 to PINT0
interrupt requests.
interrupt requests.
0: No interrupt request at PINTn pin
1: Interrupt request at PINTn pin
6 PINT6R
0 R
5 PINT5R
0 R
4 PINT4R
0 R
3 PINT3R
0 R
2 PINT2R
0 R
1 PINT1R
0 R
0 PINT0R
0 R
[Legend]
n = 7 to 0