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Renesas R5S72623 User Manual

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Section 9   Bus State Controller 
 
R01UH0134EJ0400  Rev. 4.00  
 
Page 287 of 2108 
Sep 24, 2014 
 
 
 
SH7262 Group, SH7264 Group 
9.4.7
 
Refresh Time Constant Register (RTCOR) 
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 
and RTCNT is cleared to 0. 
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. 
This request is maintained until the refresh operation is performed. If the request is not processed 
when the next matching occurs, the previous request is ignored. 
When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. 
The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit 
only affects the interrupt request and does not clear the refresh request. Therefore, a combination 
of refresh request and interval timer interrupt can be specified so that the number of refresh 
requests are counted by using timer interrupts while refresh is performed periodically. 
When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write 
protection.  
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 
 
Bit Bit 
Name 
Initial 
Value R/W  Description 
31 to 8 
 All 
0 
R 
Reserved 
These bits are always read as 0.  
7 to 0 
 
All 0 
R/W 
8-Bit Counter