Renesas R5S72623 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 475 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3.7
Timer Input Capture Control Register (TICCR)
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1
and TCNT_2 are cascaded. This module has one TICCR in channel 1.
and TCNT_2 are cascaded. This module has one TICCR in channel 1.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
-
-
-
-
I2BE
I2AE
I1BE
I1AE
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 4
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
3
I2BE
0
R/W
Input Capture Enable
Specifies whether to include the TIOC2B pin in the
TGRB_1 input capture conditions.
TGRB_1 input capture conditions.
0: Does not include the TIOC2B pin in the TGRB_1
input capture conditions
1: Includes the TIOC2B pin in the TGRB_1 input
capture conditions
2
I2AE
0
R/W
Input Capture Enable
Specifies whether to include the TIOC2A pin in the
TGRA_1 input capture conditions.
TGRA_1 input capture conditions.
0: Does not include the TIOC2A pin in the TGRA_1
input capture conditions
1: Includes the TIOC2A pin in the TGRA_1 input
capture conditions
1
I1BE
0
R/W
Input Capture Enable
Specifies whether to include the TIOC1B pin in the
TGRB_2 input capture conditions.
TGRB_2 input capture conditions.
0: Does not include the TIOC1B pin in the TGRB_2
input capture conditions
1: Includes the TIOC1B pin in the TGRB_2 input
capture conditions