Renesas R5S72623 User Manual

 

Section 11   Multi-Function Timer Pulse Unit 2 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 483 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous 
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when 
the corresponding bit in TSYR is set to 1. 

Bit:

Initial value:

R/W:

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

R/W

R/W

R

R

R

R/W

R/W

R/W

SYNC4 SYNC3

-

-

-

SYNC2 SYNC1 SYNC0

 

 

7 

SYNC4 

0 

R/W 

Timer Synchronous operation 4 and 3 

These bits are used to select whether operation is 
independent of or synchronized with other channels. 

When synchronous operation is selected, the TCNT 
synchronous presetting of multiple channels, and 
synchronous clearing by counter clearing on another 
channel, are possible. 

To set synchronous operation, the SYNC bits for at 
least two channels must be set to 1. To set 
synchronous clearing, in addition to the SYNC bit , the 
TCNT clearing source must also be set by means of 
bits CCLR0 to CCLR2 in TCR. 

0: TCNT_4 and TCNT_3 operate independently (TCNT 

presetting/clearing is unrelated to other channels) 

1: TCNT_4 and TCNT_3 performs synchronous 

operation 
TCNT synchronous presetting/synchronous clearing 
is possible 

6 SYNC3 0  R/W 

5 to 3 



 All 

0 

R 

Reserved 

These bits are always read as 0. The write value should 
always be 0.