Renesas R5S72623 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 501 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3.26
Timer Interrupt Skipping Counter (TITCNT)
TITCNT is an 8-bit readable/writable counter. This module has one TITCNT. TITCNT retains its
value even after stopping the count operation of TCNT_3 and TCNT_4.
value even after stopping the count operation of TCNT_3 and TCNT_4.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
-
3ACNT[2:0]
-
4VCNT[2:0]
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7
0
R
Reserved
This bit is always read as 0.
6 to 4
3ACNT[2:0] 000
R
TGIA_3 Interrupt Counter
While the T3AEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TGIA_3 interrupt
occurs.
these bits is incremented every time a TGIA_3 interrupt
occurs.
[Clearing conditions]
When the 3ACNT2 to 3ACNT0 value in TITCNT
matches the 3ACOR2 to 3ACOR0 value in TITCR
When the T3AEN bit in TITCR is cleared to 0
When the 3ACOR2 to 3ACOR0 bits in TITCR are
When the 3ACOR2 to 3ACOR0 bits in TITCR are
cleared to 0
3
0
R
Reserved
This bit is always read as 0.
2 to 0
4VCNT[2:0] 000
R
TCIV_4 Interrupt Counter
While the T4VEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TCIV_4 interrupt
occurs.
these bits is incremented every time a TCIV_4 interrupt
occurs.
[Clearing conditions]
When the 4VCNT2 to 4VCNT0 value in TITCNT
matches the 4VCOR2 to 4VCOR2 value in TITCR
When the T4VEN bit in TITCR is cleared to 0
When the 4VCOR2 to 4VCOR2 bits in TITCR are
When the 4VCOR2 to 4VCOR2 bits in TITCR are
cleared to 0
Note: To clear the TITCNT, clear the bits T3AEN and T4VEN in TITCR to 0.