Renesas R5S72623 User Manual
Section 14 Realtime Clock
Page 686 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
14.3.9
Second Alarm Register (RSECAR)
RSECAR is an alarm register corresponding to the BCD-coded second counter RSECCNT. When
the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincides, an alarm flag of RCR1 is set to 1.
the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincides, an alarm flag of RCR1 is set to 1.
The assignable range is from 00 through 59
ENB bits (practically in BCD), otherwise operation
errors occur.
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
0
1
2
3
4
5
6
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIt:
Initial value:
R/W:
ENB
10 seconds
1 second
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
7
ENB
Undefined R/W
When this bit is set to 1, a comparison with the
RSECCNT value is performed.
6 to 4
10 seconds
Undefined R/W
Ten's position of seconds setting value
3 to 0
1 second
Undefined R/W
One's position of seconds setting value