Renesas R5S72623 User Manual
Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00
Page 937 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
18.5
Usage Notes
18.5.1
Limitations from Underflow or Overflow during DMA Operation
If an underflow or overflow occurs while the DMA is in operation, the module should be restarted.
The transmit and receive buffers in the SSIF consists of 32-bit registers that share the L and R
channels. Therefore, data to be transmitted and received at the L channel may sometimes be
transmitted and received at the R channel if an underflow or overflow occurs, for example, under
the following condition: the control register (SSICR) has a 32-bit setting for both data word length
(DWL2 to DWL0) and system word length (SWL2 to SWL0).
The transmit and receive buffers in the SSIF consists of 32-bit registers that share the L and R
channels. Therefore, data to be transmitted and received at the L channel may sometimes be
transmitted and received at the R channel if an underflow or overflow occurs, for example, under
the following condition: the control register (SSICR) has a 32-bit setting for both data word length
(DWL2 to DWL0) and system word length (SWL2 to SWL0).
If an error occurrence is confirmed with four types of error interrupts (transmit underflow,
transmit overflow, receive underflow, and receive overflow) or the corresponding error status flag
(the bits TUIRQ, TOIRQ, RUIRQ, and ROIRQ in SSISR), write 0 to the TEN or REN bit in
SSICR to disable DMA transfer requests in this module, thus stopping the operation. (In this case,
the direct memory access controller setting should also be stopped.) After this, for receive
operation write 0 to the error status flag bit to clear the error status, make settings to the direct
memory access controller again, and restart the transfer. For transmit operation perform a software
reset, then start again from the start sequence.
transmit overflow, receive underflow, and receive overflow) or the corresponding error status flag
(the bits TUIRQ, TOIRQ, RUIRQ, and ROIRQ in SSISR), write 0 to the TEN or REN bit in
SSICR to disable DMA transfer requests in this module, thus stopping the operation. (In this case,
the direct memory access controller setting should also be stopped.) After this, for receive
operation write 0 to the error status flag bit to clear the error status, make settings to the direct
memory access controller again, and restart the transfer. For transmit operation perform a software
reset, then start again from the start sequence.
18.5.2
Note on Changing Mode from Master Transceiver to Master Receiver
If a transmit underflow occurs in master transceiver mode and the TEN bit in SSICR is set to 0 in
order to disable transmit operation, SSIWS output is broken. In order to receive seamlessly after
changing mode to master receiver mode, write dummy data to SSITDR to suppress transmit
underflow.
order to disable transmit operation, SSIWS output is broken. In order to receive seamlessly after
changing mode to master receiver mode, write dummy data to SSITDR to suppress transmit
underflow.