Renesas R5S72622 User Manual

 

Section 21   IEBus

TM

 Controller 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1101 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Internal bus interface 

Internal bus interface 

  Data width: 8 bits 
  Register access 

IEBus interface 

Interface conforms to IEBus specifications 

  Outputs data from transmit controller to IEBus in IEBus 

specification bit format 

  Picks out frame data in IEBus specification bit format to transfer 

to receive controller 

Register Control 

register 

  Register to control this module 
  Readable/writable from internal bus 

Transmit controller 

Transmits data in transmit buffer to IEBus 

  Generates transmit frame combining header information in 

register and data in transmit buffer to transmits 

  Detects transmit error 

Receive controller 

Stores data from IEBus in receive buffer 

  Stores header information and data in received frame in register 

and receive buffer, respectively 

  Detects receive error 

Transmit data buffer 

Buffer for data transmission 

  Buffer that stores data to be transmitted to IEBus 
  Buffer size: 128 bytes 

Receive data buffer 

Buffer for data reception 

  Buffer that stores data received from IEBus 
  Buffer size: 128 bytes 

 

IEBus receive data pin 

IERxD 

Input 

Receive data input pin 

IEBus transmit data pin 

IETxD 

Output 

Transmit data output pin