Renesas R5S72622 User Manual

 
Section 24   A/D Converter 

Page 1284 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

AN0 to AN7*

3 k

Ω

20 pF

To A/D converter

Note:  Values are reference values.
 

*  Only AN0 to AN3 can be used in the SH7262 Group.

 

Analog input capacitance 

 20  pF 

Allowable signal-source impedance 

 5 

k

 

 

This LSI's analog input is designed such that conversion precision is guaranteed for an input signal 
for which the signal source impedance is 5 k

 or less. This specification is provided to enable the 

A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; 
if the sensor output impedance exceeds 5 k

, charging may be insufficient and it may not be 

possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with 
a large capacitance provided externally for A/D conversion in single mode, the input load will 
essentially comprise only the internal input resistance of 3 k

, and the signal source impedance is 

ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to 
follow an analog signal with a large differential coefficient (e.g., 5 mV/

s or greater) (see  

figure 24.10). When converting a high-speed analog signal, a low-impedance buffer should be 
inserted.