Renesas R5S72622 User Manual
Section 25 NAND Flash Memory Controller
Page 1312 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 20
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
19 to 0
RBTMOUT
[19:0]
[19:0]
H'00000
R/W
Ready Busy Timeout
Specify timeout time (the number of P
clocks) in busy
state. When these bits are set to 0, timeout is not
generated.
generated.
25.3.10
Ready Busy Timeout Counter (FLBSYCNT)
FLBSYCNT is a 32-bit read-only register.
The status of flash memory obtained by the status read is stored in the bits STAT[7:0].
The timeout time set in the bits RBTMOUT[19:0] in FLBSYTMR is copied to the bits
RBTIMCNT[19:0] and counting down is started when the FRB pin is placed in a busy state. When
values in the RBTIMCNT[19:0] become 0, 1 is set to the BTOERB bit in FLINTDMACR, thus
notifying that a timeout error has occurred. In this case, an FLSTE interrupt request can be issued
if an interrupt is enabled by the RBERINTE bit in FLINTDMACR.
RBTIMCNT[19:0] and counting down is started when the FRB pin is placed in a busy state. When
values in the RBTIMCNT[19:0] become 0, 1 is set to the BTOERB bit in FLINTDMACR, thus
notifying that a timeout error has occurred. In this case, an FLSTE interrupt request can be issued
if an interrupt is enabled by the RBERINTE bit in FLINTDMACR.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
STAT[7:0]
-
-
-
-
RBTIMCNT[19:16]
RBTIMCNT[15:0]
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 24 STAT[7:0]
All 0
R
Indicate the flash memory status obtained by the status
read.
read.
23 to 20
All
0
R
Reserved
These bits are always read as 0.