Renesas R5S72622 User Manual

Page of 2152
 
Section 26   USB 2.0 Host/Function Module 
Page 1432 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
Bit Bit 
Name 
Initial 
Value R/W  Description 
9 DBLB 
0 R/W 
Double 
Buffer 
Mode 
Selects either single or double buffer mode for the 
FIFO buffer used by the selected pipe.  
0: Single buffer 
1: Double buffer 
This bit is valid when PIPE1 to PIPE5 are selected.  
When this bit has been set to 1, this module assigns 
two planes of the FIFO buffer size specified by the 
BUFSIZE bits in PIPEBUF to the selected pipe. 
Specifically, the following expression determines the 
FIFO buffer size assigned to the selected pipe by this 
module. 
(BUFSIZE + 1) 
 64  (DBLB + 1) [bytes] 
Modify these bits while CSSTS is 0 and PID is NAK 
and before the pipe is selected by the CURPIPE bits. 
To modify these bits after completing USB 
communication using the selected pipe, write 1 and 
then 0 to ACLRM continuously to clear the FIFO 
buffer assigned to the selected pipe while the 
CSSTS, PID, and CURPIPE bits are in the above-
described state. 
Before modifying these bits after modifying the PID 
bits for the selected pipe from BUF to NAK, check 
that CSSTS and PBUSY are 0. However, if the PID 
bits have been modified to NAK by this module, 
checking PBUSY is not necessary.