Renesas R5S72622 User Manual
Section 32 General Purpose I/O Ports
Page 1750 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
32.2.27
Port G Port Register 0, 1 (PGPR0, PGPR1)
PGPR1 and PGPR0 are 16-bit read-only registers, in which the PG24PR to PG0PR bits
correspond to the PG24 to PG0 pins, respectively. PGPR1 and PGPR0 always return the states of
the pins regardless of the PGCR7 to PGCR0 settings.
correspond to the PG24 to PG0 pins, respectively. PGPR1 and PGPR0 always return the states of
the pins regardless of the PGCR7 to PGCR0 settings.
(1) Port G Port Register 1 (PGPR1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PG24 PG23 PG22 PG21 PG20 PG19 PG18 PG17 PG16
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
-
-
-
-
-
-
PG24
PR
PG23
PR
PG22
PR
PG21
PR
PG20
PR
PG19
PR
PG18
PR
PG17
PR
PG16
PR
-
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Description
15 to 9
All
0 R
Reserved
These bits are always read as 0. The write
value should always be 0.
value should always be 0.
8 PG24PR
Pin
state
R
The
pin state is returned. These bits cannot be
modified.
Note:
Bits 8 to 5 are reserved in the SH7262
Group. These bits are always read as
0. The write value should always be 0.
Group. These bits are always read as
0. The write value should always be 0.
7 PG23PR
Pin
state
R
6 PG22PR
Pin
state
R
5 PG21PR
Pin
state
R
4 PG20PR
Pin
state
R
3 PG19PR
Pin
state
R
2 PG18PR
Pin
state
R
1 PG17PR
Pin
state
R
0 PG16PR
Pin
state
R