Renesas R5S72622 User Manual
Section 6 Exception Handling
Page 148 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
6.6.2
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU
operates as follows:
operates as follows:
1. The exception service routine start address which corresponds to the vector number specified
in the TRAPA instruction is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
6.6.3
Slot Illegal Instructions
An instruction placed immediately after a delayed branch instruction is called the “instruction
placed in a delay slot”. When the instruction placed in the delay slot is undefined code (including
FPU instructions and FPU-related CPU instructions in FPU module standby state), an instruction
that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a
DIVU instruction, slot illegal exception handling starts when such kind of instruction is decoded.
When the FPU has entered a module standby state, the floating point operation instruction and
FPU-related CPU instructions are handled as undefined codes. If these instructions are placed in a
delay slot and then decoded, a slot illegal instruction exception handling starts.
placed in a delay slot”. When the instruction placed in the delay slot is undefined code (including
FPU instructions and FPU-related CPU instructions in FPU module standby state), an instruction
that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a
DIVU instruction, slot illegal exception handling starts when such kind of instruction is decoded.
When the FPU has entered a module standby state, the floating point operation instruction and
FPU-related CPU instructions are handled as undefined codes. If these instructions are placed in a
delay slot and then decoded, a slot illegal instruction exception handling starts.
The CPU operates as follows:
1. The exception service routine start address is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
delayed branch instruction immediately before the undefined code, the instruction that rewrites
the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU
instruction.
the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU
instruction.
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. The jump that occurs is not a delayed branch.