Renesas R5S72622 User Manual
Section 35 Motor Control PWM Timer
Page 1844 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
35.6
Usage Note
35.6.1
Conflict between Buffer Register Write and Compare Match
If a PWBFR_n write is performed in the state immediately after a cycle register compare match,
the buffer register and duty register are both modified. PWM output changed by the cycle register
compare match is not changed by modification of the duty register due to conflict. This may result
in unanticipated duty output.
the buffer register and duty register are both modified. PWM output changed by the cycle register
compare match is not changed by modification of the duty register due to conflict. This may result
in unanticipated duty output.
Buffer register modification must be completed before automatic transfer by the direct memory
access controller, exception handling due to a compare match interrupt, or the occurrence of a
cycle register compare match on detection of the rise of CMF (compare match flag) in PWCR_n.
access controller, exception handling due to a compare match interrupt, or the occurrence of a
cycle register compare match on detection of the rise of CMF (compare match flag) in PWCR_n.
T1
Tw
Tw
T2
φ
Address
Write signal
PWCNT
(lower 10 bits)
(lower 10 bits)
PWBFR
PWDTR
PWM output
CMF
Buffer register address
Compare match
0
M
N
M
N
Figure 35.9 Conflict between Buffer Register Write and Compare Match