Renesas R5S72622 User Manual
Section 7 Interrupt Controller
R01UH0134EJ0400 Rev. 4.00
Page 171 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
7.3.8
Bank Control Register (IBCR)
IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority
level.
level.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit:
Initial value:
R/W:
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
-
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
15 E15 0 R/W
Enable
These bits enable or disable use of register banks for
interrupt priority levels 15 to 1.
interrupt priority levels 15 to 1.
0: Use of register banks is disabled
1: Use of register banks is enabled
14 E14 0 R/W
13 E13 0 R/W
12 E12 0 R/W
11 E11 0 R/W
10 E10 0 R/W
9 E9 0 R/W
8 E8 0 R/W
7 E7 0 R/W
6 E6 0 R/W
5 E5 0 R/W
4 E4 0 R/W
3 E3 0 R/W
2 E2 0 R/W
1 E1 0 R/W
0
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.