Renesas R5S72622 User Manual

 
Section 8   Cache 
 

Page 218 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

Operations for the operand cache are described here. Operations for the instruction cache are 
similar to those for the operand cache except for the address array not having the U bit, and there 
being no prefetch operation or write operation, or a write-back buffer. 

If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is 
accessed, the cache will be searched to see if the desired data is in the cache. Figure 8.2 illustrates 
the method by which the cache is searched.  

Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of 
that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits 
31 to 11 of the address used to access memory are compared with the read tag address. The 
address comparison uses all four ways. When the comparison shows a match and the selected 
entry is valid (V 

 1), a cache hit occurs. When the comparison does not show a match or the 

selected entry is not valid (V 

 0), a cache miss occurs. Figure 8.2 shows a hit on way 1.