Renesas R5S72622 User Manual
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00
Page 285 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
5 to 3
CKS[2:0]
000
R/W
Clock Select
Select the clock input to count-up the refresh timer
counter (RTCNT).
counter (RTCNT).
000: Stop the counting-up
001: B
/4
010: B
/16
011: B
/64
100: B
/256
101: B
/1024
110: B
/2048
111: B
/4096
2 to 0
RRC[2:0]
000
R/W
Refresh Count
Specify the number of continuous refresh cycles,
when the refresh request occurs after the coincidence
of the values of the refresh timer counter (RTCNT)
and the refresh time constant register (RTCOR).
These bits can make the period of occurrence of
refresh long.
when the refresh request occurs after the coincidence
of the values of the refresh timer counter (RTCNT)
and the refresh time constant register (RTCOR).
These bits can make the period of occurrence of
refresh long.
000: 1 time
001: 2 times
010: 4 times
011: 6 times
100: 8 times
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)