Renesas R5S72622 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
Page 602 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
11.7.7
Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data after write.
by the buffer operation is the data after write.
Figure 11.102 shows the timing in this case.
Address
Write signal
Compare match
signal
signal
Compare match
buffer signal
buffer signal
TGR write cycle
T1
T2
Buffer register
address
N
N
M
Buffer register write data
Buffer register
TGR
P
φ
Figure 11.102 Contention between Buffer Register Write and Compare Match