Renesas R5S72622 User Manual
Section 12 Compare Match Timer
Page 658 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
12.5
Usage Notes
12.5.1
Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 12.5 shows
the timing to clear the CMCNT counter.
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 12.5 shows
the timing to clear the CMCNT counter.
CMCNT
T1
T2
CMCNT
H'0000
N
Peripheral clock
(P
φ)
Address signal
Internal write signal
Counter clear signal
CMCSR write cycle
Figure 12.5 Conflict between Write and Compare Match Processes of CMCNT