Renesas R5S72622 User Manual
Section 17 I
2
C Bus Interface 3
R01UH0134EJ0400 Rev. 4.00
Page 891 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
17.7.4
Note on the States of Bits MST and TRN when Arbitration is Lost
When sequential bit-manipulation instructions are used to set the MST and TRS bits to select
master transmission in multi-master operation, a conflicting situation where AL in ICSR = 1 but
the mode is master transmit mode (MST = 1 and TRS = 1) may arise; this depends on the timing
of the loss of arbitration when the bit manipulation instruction for TRS is executed.
master transmission in multi-master operation, a conflicting situation where AL in ICSR = 1 but
the mode is master transmit mode (MST = 1 and TRS = 1) may arise; this depends on the timing
of the loss of arbitration when the bit manipulation instruction for TRS is executed.
This can be avoided in either of the following ways.
In multi-master operation, use the MOV instruction to set the MST and TRS bits.
When arbitration is lost, check whether the MST and TRS bits are 0. If the MST and TRS bits
When arbitration is lost, check whether the MST and TRS bits are 0. If the MST and TRS bits
have been set to a value other than 0, clear the bits to 0.
17.7.5
Note on I
2
C-bus Interface Master Receive Mode
After a master receive operation is completed, confirm the falling edge of the ninth clock cycle of
the SCL signal and generate a stop condition or regenerate a start condition.
the SCL signal and generate a stop condition or regenerate a start condition.
17.7.6
Note on IICRST and BBSY bits
When 1 is written to IICRST in ICCR2, this LSI release SCL and SDA pins. Then, if the SDA
level changes from low to high under the condition of SCL = high, BBSY in ICCR2 is cleared to 0
assuming that the stop condition has been issued.
level changes from low to high under the condition of SCL = high, BBSY in ICCR2 is cleared to 0
assuming that the stop condition has been issued.
17.7.7
Note on Issuance of Stop Conditions in Master Transmit Mode while ACKE = 1
When a stop condition is issued in master transmit mode while the ACKE bit in the I
2
C bus
interrupt enable register (ICIER) is 1, the stop condition may not be normally output depending on
the issued timing. To avoid this, recognize the falling edge of the ninth clock before issuance of
the stop condition.
the issued timing. To avoid this, recognize the falling edge of the ninth clock before issuance of
the stop condition.
The falling edge of the ninth clock can be recognized by checking the SCLO bit in the I
2
C control
register 2 (ICCR2).