Renesas R5S72622 User Manual
Section 18 Serial Sound Interface
Page 936 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
When an underflow or overflow error condition has matched, this module can be recovered to the
status before underflow or overflow condition match by using the TCHNO [1:0] and TSWNO bits
in transmission and the RCHNO[1:0] and RSWNO bits in reception. When an underflow or
overflow occurs, the host can read the channel number and system word number to determine
what point the serial audio stream has reached. In the transmitter case, the host can skip forward
through the data it wants to transmit until it finds the sample data that matches what this module is
expecting to transmit next, and so resynchronize with the audio data stream. In the receiver case
the host CPU can store null data to make the number of receive data items consistent until it is
ready to store the sample data that this module is indicating will be received next, and so
resynchronize with the audio data stream.
status before underflow or overflow condition match by using the TCHNO [1:0] and TSWNO bits
in transmission and the RCHNO[1:0] and RSWNO bits in reception. When an underflow or
overflow occurs, the host can read the channel number and system word number to determine
what point the serial audio stream has reached. In the transmitter case, the host can skip forward
through the data it wants to transmit until it finds the sample data that matches what this module is
expecting to transmit next, and so resynchronize with the audio data stream. In the receiver case
the host CPU can store null data to make the number of receive data items consistent until it is
ready to store the sample data that this module is indicating will be received next, and so
resynchronize with the audio data stream.
18.4.6
Serial Bit Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), this module is in clock slave mode and the
shift register uses the bit clock that was input to the SSISCK pin.
shift register uses the bit clock that was input to the SSISCK pin.
If the serial clock direction is set to output (SCKD = 1), this module is in clock master mode, and
the shift register uses the oversampling clock or a divided oversampling clock as the bit clock. The
oversampling clock is divided by the ratio specified by the serial oversampling clock division ratio
bits (CKDV) in SSICR for use as the bit clock by the shift register.
the shift register uses the oversampling clock or a divided oversampling clock as the bit clock. The
oversampling clock is divided by the ratio specified by the serial oversampling clock division ratio
bits (CKDV) in SSICR for use as the bit clock by the shift register.
In either case the module pin, SSISCK, is the same as the bit clock.