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Renesas R5S72624 User Manual

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Section 25   NAND Flash Memory Controller 
Page 1314 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
25.3.12
  Control Code FIFO Register (FLECFIFO) 
FLECFIFO is used to read or write the control code FIFO area. 
In DMA transfer, data in this register must be specified as the destination (source).  
Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match 
that specified in this register. When changing the read/write direction, FLECFIFO should be 
cleared by setting the AC1CLR bit in FLINTDMACR before use. 
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ECFO[31:16]
ECFO[15:0]
 
 
Bit Bit 
Name 
Initial 
Value R/W 
Description 
31 to 0 
ECFO 
[31:0] 
H'xxxxxxxx  R/W 
Control Code FIFO Area Read/Write Data 
In write: Data in this register is written to the control 
code FIFO area. 
In read: Data read from the control code FIFO area is 
stored in this register.