Renesas R5S72624 User Manual
Section 25 NAND Flash Memory Controller
Page 1332 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Figure 25.14 shows the timing of reading from the 1-Gbit large-block flash memory. During the
execution of sequential sector access spanning multiple pages, data are read from the flash
memory with the timing shown in the figure for every page (2048 + 64 bytes).
execution of sequential sector access spanning multiple pages, data are read from the flash
memory with the timing shown in the figure for every page (2048 + 64 bytes).
CE
CLE
WE
ALE
RE
IO
R/B
00h
30h
1
2
M-1
M
CA
CA
PA
PA
(0-7) (8-11) (0-7) (8-15)
M: 2112-th data
Figure 25.14 Read Timing from NAND-Type Flash Memory (Sector Access Mode)
25.4.6
ECC Error Correction
This module generates and adds ECC during write operation in sector access mode and performs
ECC error check during read operation in sector access mode. ECC processing is selectable
between 3-symbol ECC, the function provided in the earlier products, and 4-symbol ECC.
ECC error check during read operation in sector access mode. ECC processing is selectable
between 3-symbol ECC, the function provided in the earlier products, and 4-symbol ECC.
With 3-symbol ECC, only ECC generation and error detection are performed and error correction
is not performed. So, errors must be corrected by software. On the other hand, 4-symbol ECC is
capable of ECC generation, error detection, and error correction pattern generation by hardware.
is not performed. So, errors must be corrected by software. On the other hand, 4-symbol ECC is
capable of ECC generation, error detection, and error correction pattern generation by hardware.